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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a low power mixer/agc/rssi 3 v receiver if subsystem AD607 ? analog devices, inc., 1995 one technology way, p.o. box 9106, norwood. ma 02062-9106, u.s.a. tel: 617/329-4700 fax: 617/326-8703 features complete receiver on a chip: monoceiver? mixer C15 dbm 1 db compression point C8 dbm input third order intercept 500 mhz rf and lo bandwidths linear if amplifier linear-in-db gain control mgc or agc with rssi output quadrature demodulator on-board phase-locked quadrature oscillator demodulates ifs from 400 khz to 12 mhz can also demodulate am, cw, ssb low power 25 mw at 3 v cmos compatible power-down interfaces to ad7013 and ad7015 baseband converters applications gsm, cdma, tdma, and tetra receivers satellite terminals battery-powered communications receivers pin configuration 20-lead ssop (rs suffix) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD607 fdin qout iout fltr vps1 com1 prup loip ifop dmip vps2 rflo rfhi gref mxop vmid ifhi iflo gain/rs com2 general description the AD607 is a 3 v low power receiver if subsystem for opera- tion at input frequencies as high as 500 mhz and ifs from 400 khz to 12 mhz. it consists of a mixer, if amplifiers, i and q demodulators, a phase-locked quadrature oscillator, agc detector, and a biasing system with external power-down. the AD607s low noise, high intercept mixer is a doubly- balanced gilbert cell type. it has a nominal C15 dbm input referred 1 db compression point and a C8 dbm input referred third-order intercept. the mixer section of the AD607 also includes a local oscillator (lo) preamplifier, which lowers the required lo drive to C16 dbm. the gain control input can serve as either a manual gain control (mgc) input or an automatic gain control (agc) voltage- based rssi output. in mgc operation, the AD607 accepts an external gain-control voltage input from an external agc detec- tor or a dac. in agc operation, an onboard detector and an external averaging capacitor form an agc loop that holds the if output level at 300 mv. the voltage across this capacitor then provides an rssi output. the i and q demodulators provide inphase and quadrature baseband outputs to interface with analog devices ad7013 (is54, tetra, msat) and ad7015 (gsm) baseband con- verters. a quadrature vco phase-locked to the if drives the i and q demodulators. the i and q demodulators can also de- modulate am; when the AD607s quadrature vco is phase locked to the received signal, the in-phase demodulator becomes a synchronous product detector for am. the vco can also be phase-locked to an external beat-frequency oscillator (bfo), and the demodulator serves as a product detector for cw or ssb reception. finally, the AD607 can be used to demodulate bpsk using an external costas loop for carrier recovery.
AD607Cspecifications rev. 0 C2C (@ t a = + 25 c, supply = 3.0 v, if = 10.7 mhz, unless otherwise noted) model AD607ars conditions min typ max units dynamic performance mixer maxi mum rf and lo frequency range for conversion gain > 20 db 500 mhz maximum mixer input voltage for linear operation; between rfhi and rflo 54 mv input 1 db compression point rf input terminated in 50 w C15 dbm input third-order intercept rf input terminated in 50 w C5 dbm noise figure matched input, max gain, f = 83 mhz, if = 10.7 mhz 14 db matched input, max gain, f = 144 mhz, if = 10.7 mhz 12 db maximum output voltage at mxop z if = 165 w , at input compression 1.3 v mixer output bandwidth at mxop C3 db, z if = 165 w 45 mhz lo drive level mixer lo input terminated in 50 w C16 dbm lo input impedance loip to vmid 1 k w isolation, rf to if rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 30 db isolation, lo to if rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 20 db isolation, lo to rf rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 40 db isolation, if to rf rf = 240 mhz, if = 10.7 mhz, lo = 229.3 mhz 70 db if amplifiers noise figure max gain, f = 10.7 mhz 17 db input 1 db compression point if = 10.7 mhz C15 dbm output third-order intercept if = 10.7 mhz +18 dbm maximum if output voltage at ifop z if = 600 w 560 mv output resistance at ifop from ifop to vmid 15 w bandwidth C3 db at ifop, max gain 45 mhz gain control (see figures 43 and 44) gain control range mixer + if section, gref to 1.5 v 90 db gain scaling gref to 1.5 v 20 mv/db gref to general reference voltage v r 75/v r db/v gain scaling accuracy gref to 1.5 v, 80 db span 1db bias current at gain/rssi 5 m a bias current at gref 1 m a input resistance at gain, gref 1m w i and q demodulators required dc bias at dmip vpos/2 v dc input resistance at dmip from dmip to vmid 50 k w input bias current at dmip 2 m a maximum input voltage if > 3 mhz 150 mv if 3 mhz 75 mv amplitude balance if = 10.7 mhz, outputs at 600 mv p-p, f = 100 khz 0.2 db quadrature error if = 10.7 mhz, outputs at 600 mv p-p, f = 100 khz C1.2 degrees phase noise in degrees if = 10.7 mhz, f = 10 khz C100 dbc/hz demodulation gain sine wave input, baseband output 18 db maximum output voltage r l 3 20 k w 1.23 v output offset voltage measured from i out , q out to vmid 10 mv output bandwidth sine wave input, baseband output 1.5 mhz pll required dc bias at fdin vpos/2 v dc input resistance at fdin from fdin to vmid 50 k w input bias current at fdin 200 na frequency range 0.4 to 12 mhz required input drive level sine wave input at pin 1 400 mv acquisition time to 3 if = 10.7 mhz 16.5 m s power-down interface logical threshold for power up on logical high 2 v dc input current for logical high 75 m a turn-on response time to pll locked 16.5 m s standby current 550 m a power supply supply range 2.7 5.5 v supply current midgain, if = 10.7 mhz 8.5 ma operating temperature t min to t max operation to 2.7 v minimum supply voltage C25 +85 c operation to 4.5 v minimum supply voltage C40 +85 c specifications subject to change without notice.
AD607 rev. 0 C3C ordering guide temperature package package model range description option AD607ars C 25 c to +85 c 20-pin plastic rs-20 for 2.7 v to 5.5 v ssop operation; C40 c to +85 c for 4.5 v to 5.5 v operation absolute maximum ratings 1 supply voltage vps1, vps2 to com1, com2 . . . . . . . +5.5 v internal power dis sipation 2 . . . . . . . . . . . . . . . . . . . . 600 mw 2.7 v to 5.5 v operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 25 c to +85 c 4.5 v to 5.5 v operating temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C 40 c to +85 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 60 sec) . . . . . . . . +300 c notes 1 stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 thermal characteristics: 20-lead ssop package: q ja = 126 c/w. warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD607 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality.
rev. 0 C4C AD607 pin description pin mnemonic reads function 1 fdin frequency detector input pll input for i/q demodulator quadrature oscillator, 400 mv drive required from external oscillator. must be biased at v p /2. 2 com1 common #1 supply common for rf front end and main bias. 3 prup power-up input 3 v/5 v cmos compatible power-up control; logical high = powered-up; max input level = vps1 = vps2. 4 loip local oscillator input lo input, ac coupled 54 mv lo input required (C16 dbm for 50 w input termination). 5 rflo rf low input usually connected to ac ground. 6 rfhi rf high input ac coupled, 56 mv, max rf input for linear operation. 7 gref gain reference input high impedance input, typically 1.5 v, sets gain scaling. 8 mxop mixer output high impedance, single-sided current output, 1.3 v max voltage output ( 6 ma max current output). 9 vmid midsupply bias voltage output of the midsupply bias generator (vmid = vpos/2). 10 ifhi if high input ac coupled if input, 56 mv max input for linear operation. 11 iflo if low voltage reference node for if input; auto-offset null. 12 gain/rssi gain control input/rssi output high impedance input, 0 vC2 v using 3 v supply, max gain at v = 0. rssi output when using internal agc detector; rssi voltage is across agc capacitor connected to this pin. 13 com2 common #2 supply common for if stages and demodulator. 14 ifop if output low impedance, single-sided voltage output, +5 dbm ( 560 mv) max. 15 dmip demodulator input signal input to i and q demodulators 150 mv max input at if > 3 mhz for linear operation; 75 mv max input at if < 3 mhz for linear operation. must be biased at v p /2. 16 vps2 vpos supply #2 supply to high-level if, pll, and demodulators. 17 qout quadrature output low impedance q baseband output 1.23 v full scale in 20 k w min load; ac coupled. 18 iout in-phase output low impedance i baseband output; 1.23 v full scale in 20 k w min load; ac coupled. 19 fltr pll loop filter series rc pll loop filter, connected to ground. 20 vps1 vpos supply #1 supply to mixer, low level if, pll, and gain control. pin connection 20-pin ssop (rs-20) 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 top view (not to scale) AD607 fdin qout iout fltr vps1 com1 prup loip ifop dmip vps2 rflo rfhi gref mxop vmid ifhi iflo gain/rs com2
hp8656b ieee rf_out synthesizer hp8656b ieee rf_out synthesizer hp8656b ieee rf_out synthesizer hp6633a ieee vpos vneg spos sneg dcps hp34401a cpib hi lo i dmm dp8200 ieee vpos vneg spos sneg v ref hp8764b 0 0 1 1 s0 s1 v 50 w 50 w mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain hp8764b 0 0 1 1 s0 s1 v 50 w 50 w hp8594e rf_in ieee spec an hp8765b 0 1 c s0 s1 v r5 1k w characterization board hp8765b 0 1c s0 s1 v p6205 x10 out fet probe tek1105 in1 out1 in2 out2 probe supply figure 1. mixer/amplifier test set hp346b 28v noise noise source hp8656b ieee rf_out synthesizer mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain hp8765b 0 1 c s0 s1 v 50 w characterization board hp8765b 0 1c s0 s1 v hp8720c ieee_488 port_1 port_2 network an hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp8970a rf_in 28v_out noise figure meter figure 2. mixer noise figure test set typical performance characteristicsCAD607 rev. 0 C5C
rev. 0 C6C AD607 hp346b 28v noise noise source mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp8970a rf_in 28v_out noise figure meter p6205 x10 out fet probe tek1103 in1 out1 in2 out2 probe supply figure 3. if amp noise figure test set mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp8764b 0 0 1 1 s0 s1 v 50 w 50 w hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp3326a ieee output_1 output_2 dual synthesizer dcfm hp8656b ieee rf_out synthesizer p6205 x10 fet probe p6205 x10 fet probe out out 1103 out1 out2 probe supply hp8765b 0 1 c s0 s1 v hp8765b 0 1c s0 s1 v hp8694e rf_in ieee spec an hp54120 ch1 digital oscilloscope ch2 ch3 ch4 trig ieee_488 in1 in2 figure 4. pll/demodulator test set
AD607 rev. 0 C7C dp8200 ieee vpos vneg spos sneg v ref hp34401a gpib hi lo i dmm hp6633a ieee vpos vneg spos sneg dcps r1 499k w mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board figure 5. gain pin bias test set dp8200 ieee vpos vneg spos sneg v ref hp34401a gpib hi lo i dmm hp6633a ieee vpos vneg spos sneg dcps r1 499k w mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board figure 6. demodulator bias test set hp6633a ieee vpos vneg spos sneg dcps hp34401a gpib hi lo i dmm hp6633a ieee vpos vneg spos sneg dcps r1 10k w mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp3325b ieee rf_out synthesizer hp8594e rf_in ieee spec an figure 7. power-up threshold test set
rev. 0 C8C AD607 mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp54120 ch1 ch2 ch3 ch4 trig ieee_488 p6205 x10 out fet probe 1103 in1 out1 in2 out2 probe supply hp6633a ieee vpos vneg spos sneg dcps fl6082a rf_out ieee p6205 x10 out fet probe mod_out 50 w digital oscilloscope note: must be 3 resistor power divider dp8200 ieee vpos vneg spos sneg v ref hp8112 pulse_out ieee pulse generator figure 8. power-up test set mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp8594e rf_in ieee spec an p6205 x10 out fet probe 1103 in1 out1 in2 out2 probe supply hp6633a ieee vpos vneg spos sneg dcps hp8656b rf_out ieee synthesizer r1 1k figure 9. if output impedance test set mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref p6205 x10 fet probe p6205 x10 fet probe out out 1103 out1 out2 probe supply hp54120 ch1 digital oscilloscope ch2 ch3 ch4 trig ieee_488 in1 in2 fl6082a ieee rf_out mod_out characterization board 20 db figure 10. pll settling time test set
AD607 rev. 0 C9C mxop rfhi loip l r x ifop ifhi pll iout qout dmip fdin bias vpos prup gain characterization board hp6633a ieee vpos vneg spos sneg dcps dp8200 ieee vpos vneg spos sneg v ref hp3326 ieee output_1 output_2 dual synthesizer dcfm hp3325b ieee rf_out synthesizer p6205 x10 fet probe p6205 x10 fet probe out out 1103 out1 out2 probe supply hp8765b 0 1c s0 s1 v hp8694e rf_in ieee spec an in1 in2 figure 11. quadrature accuracy test set 14 13 12 11 17 16 15 20 19 18 10 9 8 1 2 3 4 7 6 5 AD607 fdin qout iout fltr vps1 com1 prup loip ifop dmip vps2 rflo rfhi gref mxop vmid ifhi iflo gain com2 0.1? c13 c15 0.1? iout * qout * ifop * gain * dmip * 0.1? c1 c3 10nf r1 1k r2 316 c6 0.1? c8 0.1? c5 1nf 4.99k r10 r8 51.1 c11 10nf r7 51.1 c10 1nf r6 51.1 c9 1nf r14 54.9 r13 301 332 r5 0.1? vpos gnd fdin prup loip rfhi mxop * ifhi 0 r12 c16 1nf 51.1 r9 c7 1nf 0.1? c2 note: connections marked * are dc coupled. figure 12. AD607 characterization board
rev. 0 C10C AD607 rf frequency ?mhz ssb nf ?db 20 18 10 50 250 70 90 110 130 150 170 190 210 230 16 14 12 19 17 15 13 11 vpos = 5v, if = 20 mhz vpos = 3v, if = 20 mhz vpos = 5v, if = 10 mhz vpos = 3v, if = 10 mhz figure 13. mixer noise figure vs. frequency 4500 3000 0 500 250 0 2500 2000 3500 4000 frequency ?mhz 1500 1000 500 50 100 150 200 300 350 400 450 resistance ? w r shunt component c shunt component 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 capacitance ?pf figure 14. mixer input impedance vs. frequency, vpos = 3 v, v gain = 0.8 v 30 20 ?0 600 300 0 25 10 15 0 5 radio frequency ?mhz ? ?5 ?0 50 100 150 200 250 350 400 450 500 550 conversion gain ?db v gain = 0.00v v gain = 0.54v v gain = 1.08v v gain = 1.62v v gain = 2.16v figure 15. mixer conversion gain vs. frequency, t = +25 c, vpos = 2.7 v, vref = 1.35 v, if = 10.7 mhz 30 20 100 0.1 25 10 15 0 5 intermediate frequency ?mhz ? ?0 110 conversion gain ?db v gain = 0.3v v gain = 0.6v v gain = 1.8v v gain = 1.2v v gain = 2.4v figure 16. mixer conversion gain vs. if, t = +25 c, vpos = 3 v, vref = 1.5 v 80 60 130 ?0 70 40 50 20 30 temperature ? c 10 ?0 70 0 ?0 ?0 ?0 10 20 30 40 50 60 80 90 100 110 120 ?0 ?0 0 gain ?db cubic fit of conv_gain (temp) cubic fit of if_gain (temp) if amp gain mixer cg figure 17. mixer conversion gain and if amplifier gain vs. te mperature, vpos = 3 v, vgain = 0.3 v, vref = 1.5 v, if = 10.7 mhz, rf = 250 mhz 80 60 6 2.4 70 40 50 20 30 supply ?volts 10 4.8 gain ?db 2.8 3.2 3.6 3.8 4 4.2 4.4 4.6 5 5.2 5.4 5.6 5.8 2.6 3 3.4 cubic fit of conv_gain (v pos ) cubic fit of if_gain (v pos ) if amp gain mixer cg figure 18. mixer conversion gain and if amplifier gain vs. supply volta ge, t = +25 c, vgain = 0.3 v, vref = 1.5 v, if = 10.7 mhz, rf = 250 mhz
AD607 rev. 0 C11C 70 50 100 0.1 60 30 40 10 20 intermediate frequency ?mhz 0 ?0 110 if amplifier gain ?db v gain = 0.3v v gain = 0.6v v gain = 1.8v v gain = 1.2v v gain = 2.4v 80 figure 19. if amplifier gain vs. frequency, t = +25 c, vpos = 3 v, vref = 1.5 v 8 4 3 0 6 0 2 ? ? gain voltage ?volts ? ?0 12 error ?db 10 ? 0.2 0.4 0.6 0.8 1.2 1.4 1.6 1.8 2.2 2.4 2.6 2.8 if amp mixer figure 20. AD607 gain error vs. gain control voltage, representative part 996.200 ? 1.00870 ms 1.02120 ms timebase = 2.5 ?/div delay = 1.00870 ms memory 1 = 100.0 mvolts/div offset = 127.3 mvolts timebase = 2.50 ?/div delay = 1.00870 ms memory 2 = 20.00 mvolts/div offset = 155.2 mvolts timebase = 2.50 ?/div delay = 1.00870 ms delta t = 16.5199 ? start = 1.00048 ms stop = 1.01700 ms trigger on external at pos. edge at 134.0 mvolts figure 21. pll acquisition time 1.00e+07 1.00e+02 ?10.00 ?00.00 ?30.00 ?20.00 carrier frequency offset, f(fm) ?hz ?40.00 ?50.00 1.00e+03 1.00e+05 ?0.00 1.00e+04 1.00e+06 phase noise ?dbc figure 22. pll phase noise l (f) vs. frequency, vpos = 3 v, c3 = 0.1 m f, if = 10.7 mhz 100 0.1 2 pll frequency ?mhz 1.5 110 fltr pin voltage ?volts 2.5 figure 23. pll loop voltage at fltr (k vco ) vs. frequency 8 5 94 85 7 3 4 1 2 quadrature angle ?degrees 0 91 86 87 88 89 90 92 93 6 95 count figure 24. demodulator quadrature angle, histogram, t = +25 c, vpos = 3 v, if = 10.7 mhz
rev. 0 C12C AD607 30 20 ? 25 10 15 5 iq gain balance ?db 0 count ? 0 1 2 figure 25. demodulator gain balance, histogram, t = +25 c, vpos = 3 v, if = 10.7 mhz 20 18 0 19 16 17 15 baseband frequency ?mhz 10 0.2 0.4 0.6 0.8 14 12 13 11 1.0 1.2 1.4 1.6 1.8 2.0 igain ?db quadratic fit of i_gain_corr (iff) i_gain_corr figure 26. demodulator gain vs. frequency 20 18 ?0 19 16 17 15 temperature ? c 10 ?0 ?0 ?0 ?0 14 12 13 11 0 1020304050 igain ?db cubic fit of i_gain_corr (temp) i_gain_corr 60 70 80 90 100 110 120 130 figure 27. demodulator gain vs. temperature 20 18 2.5 19 16 17 15 supply ?volts 10 3 14 12 13 11 3.5 4 4.5 igain ?db cubic fit of i_gain_corr (temp) i_gain_corr 5 5.5 6 figure 28. demodulator gain vs. supply voltage 40 25 17 35 15 20 10 demodulator gain ?db 0 17.2 5 17.4 17.6 17.8 18 18.2 18.4 count 18.6 18.8 30 figure 29. demodulator gain histogram, t = +25 c, vpos = 3 v, if = 10.7 mhz 12 6 ?.1 10 4 output offset ?volts 0 count ?.08 2 ?.06 ?.04 ?.02 0 0.04 0.06 0.08 0.1 8 0.02 14 figure 30. demodulator output offset voltage histogram, t = +25 c, vpos = 3 v, if = 10.7 mhz
AD607 rev. 0 C13C timebase = 5.00 ?/div delay = 40.2377 ms memory 1 = 100.0 mvolts/div offset = 154.0 mvolts timebase = 5.00 ?/div delay = 40.2377 ms memory 2 = 60.00 mvolts/div offset = 209.0 mvolts timebase = 5.00 ?/div delay = 40.2377 ms delta t = 15.7990 ? start = 40.2327 ms stop = 40.2485 ms trigger on external at pos. edge at 40.0 mvolts 40.2377 ms 40.2127 ms 40.2627 ms figure 31. power-up response time to pll stable 0 gain voltage ?volts 5 0.5 1.5 2 10 1 15 2.5 supply current ?ma figure 32. power supply current vs. gain control voltage, gref = 1.5 v product overview the AD607 provides most of the active circuitry required to realize a complete low power, single-conversion superhetero- dyne receiver, or most of a double-conversion receiver, at input frequencies up to 500 mhz, and with an if of from 400 khz to 12 mhz. the internal i/q demodulators, and their associated phase locked-loop, which can provide carrier recovery from the if, support a wide variety of modulation modes, including n- psk, n-qam, and am. a single positive supply voltage of 3 v is required (2.7 v minimum, 5.5 v maximum) at a typical sup- ply current of 8.5 ma at midgain. in the following discussion, v p will be used to denote the power supply voltage, which will be assumed to be 3 v. figure 33 shows the main sections of the AD607. it consists of a variable-gain uhf mixer and linear four-stage if strip, which together provide a voltage controlled gain range of more than 90 db; followed by dual demodulators, each comprising a multi- plier followed by a 2-pole, 2 mhz low-pass filter; and driven by a phase-locked loop providing the inphase and quadrature clocks. an internal agc detector is included, and the tempera- ture stable gain control system provides an accurate rssi capa- bility. a biasing system with cmos compatible power-down completes the AD607. mixer the uhf mixer is an improved gilbert cell design, and can operate from low frequencies (it is internally dc-coupled) up to an rf input of 500 mhz. the dynamic range at the input of the mixer is determined, at the upper end, by the maximum input signal level of 56 mv between rfhi and rflo up to which the mixer remains linear, and, at the lower end, by the noise level. it is customary to define the linearity of a mixer in terms of the 1 db gain-compression point and third-order intercept, which for the AD607 are C15 dbm and C8 dbm, respectively, in a 50 w system. figure 33. functional block diagram rfhi rflo iflo bpf loip mxop mid-point bias generator vmid ifhi bias generator vps1 vps2 prup com1 com2 vmid agc detector ptat voltage ifop bpf or lpf dmip iout fdin fltr qout gain/rssi AD607 gref vqfo
rev. 0 C14C AD607 table i. AD607 filter termination resistor values for common ifs filter filter termination resistor if impedance values 1 for 24 db of mixer gain r1 r2 r3 450 khz 1500 w 174 w 1330 w 1500 w 455 khz 1500 w 174 w 1330 w 1500 w 6.5 mhz 1000 w 215 w 787 w 1000 w 10.7 mhz 330 w 330 w 0 w 330 w notes 1 resistor values were calculated such that r1+ r2 = z filter and r1 i (r2 + z filter ) = 165 w . the maximum permissible signal level at mxop is determined by both voltage and current limitations. using a 3 v supply and vmid at 1.5 v, the maximum swing is about 1.3 v. to attain a voltage swing of 1 v in the standard if filter load of 165 w load requires a peak drive current of about 6 ma, which is well within the linear capability of the mixer. however, these upper limits for voltage and current should not be confused with issues related to the mixer gain, already discussed. in an operational system, the agc voltage will determine the mixer gain, and hence the signal level at the if input pin ifhi; it will always be less than 56 mv (C15 dbm into 50 w ), which is the limit of the if amplifiers linear range. if amplifier most of the gain in the AD607 arises in the if amplifier strip, which comprises four stages. the first three are fully differential and each has a gain span of 25 db for the nominal agc voltage range. thus, in conjunction with the mixers variable gain, the total gain exceeds 90 db. the final if stage has a fixed gain of 20 db, and it also provides differential to single-en ded conversion. the if input is differential, at ifhi (noninverting relative to the output ifop) and iflo (inverting). figure 36 shows a simpli- fied schematic of the if interface. the offset voltage of this stage would cause a large dc output error at high gain, so it is nulled by a low-pass feedback path from the if output, also shown in figure 25. unlike the mixer output, the signal at ifop is a low-impedance single-sided voltage, centered at v p /2 by the dc feedback loop. it may be loaded by a resistance as low as 50 w which will normally be connected to vmid. 10k w 10k w vmid AD607 ifhi iflo offset feedback loop ifop figure 36. simplified schematic of the if interface the mixers rf input port is differential, that is, pin rflo is functionally identical to rfhi, and these nodes are internally biased; we will generally assume that rflo is decoupled to ac ground. the rf port can be modeled as a parallel rc circuit as shown in figure 34. r in c in c2 c1 c3 l1 rfhi rflo AD607 c1, c2, l1: optional matching circuit c3: couples rflo to ac ground figure 34. mixer port modeled as a parallel rc network; an optional matching network is also shown the local oscillator (lo) input is internally biased at v p /2 via a nominal 1000 w resistor internally connected from pin loip to vmid. the lo interface includes a preamplifier which mini- mizes the drive requirements, thus simplifying the oscillator de- sign and reducing lo leakage from the rf port. internally, this single-sided input is actually differential; the noninverting input is referenced to pin vmid. the lo requires a single-sided drive of 50 mv, or C16 dbm in a 50 w system. the mixers output passes through both a low-pass filter and a buffer, which provides an internal differential to single-ended signal conversion with a bandwidth of approximately 45 mhz. its output at pin mxop is in the form of a single-ended current. this approach eliminates the 6 db voltage loss of the usual se- ries termination by replacing it with shunt terminations at the both the input and the output of the filter. the nominal conver- sion gain is specified for operation into a total if bandpass filter (bpf) load of 165 w , that is, a 330 w filter, doubly-terminated as shown in figure 33. note that these loads are connected to bias point vmid, which is always at the midpoint of the supply (that is, v p /2). the conversion gain is measured between the mixer input and the input of this filter, and varies between 1.5 db and 26.5 db for a 165 w load impedance. using filters of higher impedance, the conversion gain can always be maintained at its specified value or made even higher; for filters of lower impedance, of say z o , the conversion gain will be lowered by 10 log 10 (165/z o ). thus, the use of a 50 w filter will result in a conversion gain that is 5.2 db lower. figure 35 shows filter matching networks and table i lists resistor values. iflo bpf mxop vmid ifhi 10 11 8 9 1nf 100nf r3 100nf r1 r2 figure 35. suggested if filter matching network. the values of r1 and r2 are selected to keep the impedance at pin mxop at 165 w
AD607 rev. 0 C15C the ifs small-signal bandwidth is approximately 45 mhz from ifhi and iflo through ifop. the peak output at ifop is 560 mv at v p = 3 v and 400 mv at the minimum v p of 2.7 v. this allows some headroom at the demodulator inputs (pin dmip), which accept a maximum input of 150 mv for ifs > 3 mhz and 75 mv for ifs 3 mhz (at ifs 3 mhz, the drive to the demodulators must be reduced to avoid saturat- ing the output amplifiers with higher order mixing products that are no longer removed by the onboard low-pass filters). if the internal agc detector is used, the if output will be at an amplitude of v p /10, that is, 300 mv for v p = 3 v. this 300 mv level requires the insertion of 6 db of post-if filter loss be- tween ifop and dmip to avoid overloading the demodulators; often, a simple rc low-pass filter with its corner frequency at the if will suffice. since th ere is no band-limiting in the if strip, the output- referred noise can be quite high; in a typical application and at a gain of 75 db it is about 100 mv rms, making post-if filtering desirable. ifop may be also used as an if output for driving an a/d converter, external demodulator, or external agc detector. figure 37 shows methods of matching the optional second if filter. AD607 bpf ifop dmip r t 2r t 2r t vpos a. biasing dmip from power supply (assumes bpf ac coupled internally) AD607 bpf ifop dmip r t vmid r t c bypass b. biasing dmip from vmid (assumes bpf ac coupled internally) figure 37. input and output matching of the optional second if filter gain scaling and rssi the AD607s overall gain, expressed in decibels, is linear-in-db with respect to the agc voltage v g at pin gain/rssi. the gain of all sections is maximum when v g is zero, and reduces progressively up to v g = 2.2 v (for v p = 3 v; in general, up to a limit v p C 0.8 v). the gain of all stages changes in parallel. the AD607 features temperature-compensation of the gain scaling. note that gain/rssi pin is either an mgc input, when the gain is controlled by some external means, or an rssi output, when the internal agc detector is used. the gain control scaling is proportional to the reference voltage applied to the pin gref. when this pin is tied to the midpoint of the supply (vmid), the scale is nominally 20 mv/db (50 db/ v) for v p = 3 v. under these conditions, the lower 80 db of gain range (mixer plus if) corresponds to a control voltage of 0.4 v v g 2.0 v. the final centering of this 1.6 v range de- pends on the insertion losses of the if filters used. more gener- ally, the gain scaling using these connections is v p /150 (volts per db), so becomes 33.3 mv/db (30 db/v) using a 5 v supply, with a proportional change in the agc range, to 0.33 v v g 3 v, table ii lists gain control voltages and scale factors for power supply voltages from 2.7 v to 5.5 v. alternatively, pin gref can be tied to an external voltage reference, v r , provided, for example, by an ad1582 (2.5 v) or ad1580 (1.21 v) voltage reference, to provide supply- independent gain scaling of v r /75 (volts per db). when using the analog devices ad7013 and ad7015 baseband converters, the external reference may also be provided by the reference output of the baseband converter (figure 38). for example, the ad7015 baseband converter provides a v r of 1.23 v; when connected to gref the gain scaling is 16.4 mv/db (60 db/v). an auxiliary dac in the ad7015 can be used to generate the mgc voltage. since it uses the same reference voltage, the nu- merical input to this dac provides an accurate rssi value in digital form, no longer requiring the reference voltage to have high absolute accuracy. AD607 iout r qout r c c vmid gref 10nf gain/rssi 1nf ad7013 or ad7015 iadc qadc iadc qadc refout bypass (ad7015) (ad7013) aux dac figure 38. interfacing the AD607 to the ad7013 or ad7015 baseband converters i/q demodulators both demodulators (i and q) receive their inputs at pin dmip. internally, this single-sided input is actually differential; the noninverting input is referenced to pin vmid. each demodula- tor comprises a full-wave synchronous detector followed by a 2 mhz, two-pole low-pass filter, producing single-sided outputs at pins iout and qot. using the i and q demodulators for ifs above 12 mhz is precluded by the 400 khz to 12 mhz response of the pll used in the demodulator section. pin dmip requires an external bias source at v p /2; figure 39 shows sug- gested methods. outputs iout and qout are centered at v p /2 and can swing up to 1.23 v even at the low supply voltage of 2.7 v. they can therefore directly drive the rx adcs in the ad7015 baseband converter, which require an amplitude of 1.23 v to fully load them when driven by a single-sided signal. the con- version gain of the i and q demodulators is 18 db (x8), requir- ing a maximum input amplitude at dmip of 150 mv for ifs > 3 mhz.
rev. 0 C16C AD607 table ii. AD607 gain and manual gain control voltage vs. power supply voltage power supply gref gain control voltage (= vmid) scale factor scale factor voltage input range (v) (v) (db/v) (mv/db) (v) 2.7 1.35 55.56 18.00 0.360C1.800 3.0 1.5 50.00 20.00 0.400C2.000 3.5 1.75 42.86 23.33 0.467C2.333 4.0 2.0 37.50 26.67 0.533C2.667 4.5 2.25 33.33 30.00 0.600C3.000 5.0 2.5 30.00 33.33 0.667C3.333 5.5 2.75 27.27 36.67 0.733C3.667 note maximum gain occurs for gain control voltage = 0 v. AD607 bpf ifop dmip r t 2r t 2r t vpos a. biasing dmip from power supply (assumes bpf ac coupled internally) AD607 bpf ifop dmip r t dmip r t c bypass b. biasing dmip from vmid (assumes bpf ac coupled internally) figure 39. suggested methods for biasing pin dmip at v p /2 for ifs < 3 mhz, the on-chip low-pass filters (2 mhz cutoff) do not attenuate the if or feedthrough products; thus, the maxi- mum input voltage at dmip must be limited to 75 mv to al- low sufficient headroom at the i and q outputs for not only the desired baseband signal but also the unattenuated higher-order demodulation products. these products can be removed by an external low-pass filter. in the case of is54 applications using a 455 khz if and the ad7013 baseband converter, a simple 1-pole rc filter with its corner above the modulation bandwidth is sufficient to attenuate undesired outputs. phase-locked loop the demodulators are driven by quadrature signals that are pro- vided by a variable frequency quadrature oscillator (vfqo), phase locked to a reference signal applied to pin fdin. when this signal is at the if, inphase and quadrature baseband out- puts are generated at iout and qout, respectively. the the reference signal may be provided from an external source, in the form of a high-level clock, typically a low level signal ( 400 mv) since there is an input amplifier between fdin and the loops phase detector. for example, the if output itself can be used by connecting dmip to fdin, which will then pro- vide automatic carrier recover for synchronous am detection and take advantage of any post-if filtering. pin fdin must be biased at v p /2; figure 41 shows suggested methods. the vfqo operates from 400 khz to 12 mhz and is con- trolled by the voltage between vpos and fltr. in normal op- eration, a series rc network, forming the pll loop filter, is connected from fltr to ground. the use of an integral sample-hold system ensures that the frequency-control voltage on pin fltr remains held during power-down, so reacquisition of the carrier typically occurs in 16.5 m s. in practice, the probability of a phase mismatch at power-up is high, so the worst-case linear settling period to full lock needs to be considered in making filter choices. this is typically 16.5 m s at an if of 10.7 mhz for a 100 mv signal at dmip and fdin. quadrature accuracy of this vfqo is typically C1.2 at 10.7 mhz. the pll uses a sequential-phase detector that comprises low power emitter-coupled logic and a charge pump (figure 40). sequential phase detector variable- frequency quadrature oscillator 90 q-clock (ecl outputs) i-clock reference carrier (fdin after limiting) u d i u ~ 40? c r v f f r i d ~ 40? figure 40. simplified schematic of the pll and quadrature vco
AD607 rev. 0 C17C bias system the AD607 operates from a single supply, v p , usually of 3 v, at a typical supply current of 8.5 ma at midgain and t = 27 c, corresponding to a power consumption of 25 mw. any voltage from 2.7 v to 5.5 v may be used. the bias system in cludes a fast-acting active-high cmos- compatible power-up switch, allowing the part to idle at 550 m a when disabled. biasing is proportional-to-absolute-temperature (ptat) to ensure stable gain with temperature. an independent regulator generates a voltage at the midpoint of the supply (v p /2) which appears at the vmid pin, at a low im- pedance. this voltage does not shut down, ensuring that the major signal interfaces (e.g., mixer-to-if and if-to-demodula- tors) remain biased at all times, thus minimizing transient dis- turbances at power-up and allowing the use of substantial decoupling capacitors on this node. the quiescent consumption of this regulator is included in the idling current. AD607 fdin 50k w 50k w vpos external frequency reference a. biasing fdin from supply when using external frequency reference AD607 fdin 50k w c bypass external frequency reference vmid b. biasing fdin from vmid when using external frequency reference figure 41. suggested methods for biasing pin fdin at v p /2 using the AD607 in this section, we will focus on a few areas of special impor- tance and include a few general application tips. as is true of any wideband high gain component, great care is needed in pc board layout. the location of the particular grounding points must be considered with due regard to possibility of unwanted signal coupling, particularly from ifop to rfhi or ifhi or both. the high sensitivity of the AD607 leads to the possibility that unwanted local em signals may have an effect on the perfor- mance. during system development, carefully-shielded test as- semblies should be used. the best solution is to use a fully- enclosed box enclosing all components, with the minimum number of needed signal connectors (rf, lo, i and q outputs) in miniature coax form. the i and q output leads can include small series resistors (about 100 w ) inside the shielded box without significant loss of performance, provided the external loading during testing is light (that is, a resistive load of more than 20 k w and capaci- tances of a few picofarads). these help to keep unwanted rf emanations out of the interior. the power supply should be connected via a through-hole ca- pacitor with a ferrite bead on both inside and outside leads. close to the ic pins, two capacitors of different value should be used to decouple the main supply (v p ) and the midpoint supply pin, vmid. guidance on these matters is also generally in- cluded in applications schematics. gain distribution as in all receivers, the most critical decisions in effectively using the AD607 relate to the partitioning of gain between the various subsections (mixer, if amplifier, demodulators) and the place- ment of filters, so as to achieve the highest overall signal-to- noise ratio and lowest intermodulation distortion. figure 42 shows the main rf/if signal path at maximum and minimum signal levels. figure 42. signal levels for minimum and maximum gain iout qout i q rfhi loip mxop ifhi dmip ifop if bpf if bpf (vmid) 330 w 330 w (typical impedance) (location of optional second if filter) constant ?6dbm ( 50mv) 54mv max input 1.3v max output 54mv max input 560mv max output 154mv max input 1.23v max output
rev. 0 C18C AD607 as noted earlier, the gain in db is reduced linearly with the volt- age v g on the gain pin. figure 43 shows how the mixer and if strip gains vary with v g when gref is connected to vmid (1.5 v) and a supply voltage of 3 v is used. figure 44 shows how these vary when gref is connected to a 1.23 v reference. v g (7.5db) (1.5db) 01v2v 0.4v 1.8v 2.2v (67.5db) (21.5db) if gain mixer gain 90db 80db 70db 60db 50db 40db 30db 20db 10db 0db normal operating range figure 43. gain distribution for gref = 1.5 v (7.5db) (1.5db) 01v2v (67.5db) (21.5db) if gain mixer gain 90db 80db 70db 60db 50db 40db 30db 20db 10db 0db 0.328v 1.64v v g normal operating range figure 44. gain distribution for gref = 1.23 v using the internal agc detector the AD607 includes a detector cell at the output of the if am- plifier that allows it to provide its own agc and output-leveling function in receiver applications where dsp support is not needed. it is only necessary to connect a filter capacitor between the gain pin and ground to invoke this feature. the voltage appearing on this pin may then be used as an rssi output, with the scaling discussed earlier; note particularly that the voltage on gref continues to determine this scaling. figure 45 shows a simplified schematic of the detector. transis- tor q2 remains cut off by a 300 mv bias (when v p = 3 v; in gen- eral, ? v p /10) until the positive tip of the if waveform causes it to briefly conduct, charging the agc filter capacitor c agc in a positive direction. the voltage across this capacitor is v g . last if stage ifop 1.5v if output q1 q2 77? 30? 4.5? zero 1.5v + 316mv i c 2 gain to internal gain control cagc (ext) 4.5? (int) comm average of ic2 is forced to 4.5? by integration in cagc figure 45. simplified schematic of agc detector acting against this is an internally generated 4.5 m a pull-down current, which operates to within a few millivolts of ground. as v g, the voltage at the gain/rssi pin, rises, the gain falls, so re- ducing the amplitude of the if output and reducing the ampli- tude of the current spike in q2; eventually a point is reached where its average collector current is balanced by the pull-down current, and the charging ceases. it will be apparent that the loop filter is essentially a perfect integrator. this simple system can be used because the input impedance of the gain-control system, also internally tied to the gain/rssi pin, is several megohms, and its bias current is small. the volt- age v g may be used as an rssi output; however, if it is to be heavily loaded, a buffer amplifier must be used. note that, unlike a post-demodulation agc detector (via dsp), this scheme responds to signal plus noise. thus, when operating at high gains, the agc loop will see a substantial output at the ifop node, even though a filter may be added by the user between the pins ifop and dmip. this will trick the loop into lowering the gain until the composite output signal (if plus noise) reaches the reference level and satisfies the average- current requirement. in these circumstances, the wanted signal will be smaller than expected. thus, the internal agc system will result in a slight compression of the demodulated output for very small signal levels. agc discharge time the discharge current is approximately 4.5 m a; thus, to restore gain in the event of a rapid drop-out requires a time of t = c v g /4.5 m a. using a 1 nf capacitor, and noting that an 80 db gain change corresponds to 1.6 v, the discharge time is 355 m s. note, however, that when gref is tied to a different value, the scaling changes. for gref = 1.23 v, the scale factor is 16.4 mv/db, 80 db corresponds to a 1.312 v change, and the discharge time decreases to 290 m s. v g could also be expressed in db: with a scaling of 20 mv/db, it works out to t = c p 44,000, where p is the change in input power, expressed in db. thus, using c = 1 nf, checking the time needed for 80 db we get t = 355 m s. for the case where the scaling is 16.4 mv/db, t = c p 36,000. the AD607s agc detector delivers only one brief charging pulse per cycle of the if. at a 10.7 mhz if, for example, this is every 93 ns. when the agc system is in equilibrium, this pulse
AD607 rev. 0 C19C of current exactly balances the 4.5 m a discharge current. (it makes no difference what the actual value of v g is at that point, since the agc filter is an integrator.) thus, at 20 mv/db v ripple = it c = 4.5 m a 93 ns 1 nf = 0. 42 mv this corresponds to 0.021 db, and the ripple will modulate the gain by that amount over each cycle. the effect of such modula- tion on the signal is hard to quantify, but it roughly translates to a 2% amplitude modulation. also, the gain ripple depends on the scale factor. for this example, at gref = 1.23 v and a 16.4 mv/db scale factor, the gain ripple increases to 0.025 db. agc charge time when the gain is too high, the if amplifier will be overdriven to produce a square wave output (roughly) of 560 mv. if per- fectly square and time- and amplitude-symmetric, this would be sliced at the 300 mv level to generate a current of 76 m a/2, or 38 m a. after subtracting the 4.5 m a, we should have about 33 m a. in fact, the maximum ramp-up current is about 20 m a, because the waveform is not a crisp square wave (and as the loop ap- proaches equilibrium it is more nearly sinusoidal). thus, the ramp-up rate is 20/4.5 = 4.4 times faster than the discharge rate. in our example, a 1.6 v change will require about 1.5 ms using c = 1 nf. applications hints do not place a resistor from pin 12 to ground: the resistor converts the integratorideal for agcinto a low-pass filter. an integrator needs no input to sustain a given output; a low- pass filter does. this input is an increased amplitude required at ifop. the agc loop thus does not level the output at ifop. reasons for using a larger agc capacitor 1. in applications where gain modulation may be troublesome, raise the capacitor from 1 nf to 2.7 nf; the 80 db slew time (at 20 mv/db) is now close to 1 ms. 2. as the if is lowered, the capacitor must be increased accord- ingly if gain ripple is to be avoided. thus, to achieve the same ripple at 455 khz requires the 1 nf capacitor to be in- creased to 0.022 m f. 3. in am applications, the agc loop must not track the modu- lation envelope. the objective should be that the gain should not vary by more than the amount required to introduce, say, 1% thd distortion at the lowest modulation frequency, say, 300 hz. note that in am applications it is the modulation bandwidth that determines the required agc filter capaci- tor, not the if. 4. in some applications, even slower agc may be desired than that required to prevent modulation tracking. AD607 evaluation board the AD607 evaluation board (figures 46 and 47) consists of an AD607, ground plane, i/o connectors, and a 10.7 mhz band- pass filter. the rf and lo ports are terminated in 50 w to provide a broadband match to external signal generators to al- low a choice of rf and lo input frequencies. the if filter is at 10.7 mhz and has 330 w input and output terminations; the board is laid out to allow the user to substitute other filters for other ifs. figure 46. evaluation board fdin com1 prup loip rflo rfhi gref mxop vmid ifhi vps1 fltr iout qout vps2 dmip ifop com2 gain iflo AD607 c12 0.1? r9 0 c5 1nf c6 0.1? c8 0.1? rssi if q i c1 0.1? c3 10nf r1 1k w c2 0.1? c4 47pf r2 316 w c15 0.1? jumper jumper c16 1nf r10 4.99k w r11 open c11 10nf r8 51.1 w c13 0 c14 0 r7 51.1 w r6 51.1 w c10 1nf c9 1nf r5 332 w r3 332 w r4 0 c7 1nf vpos gnd fdin prup lo rf r13 50k w r15 50k w vpos fdin r12 open vmid c17 10nf c18 short r14 51.1 w fdin mod for large magnitude ac coupled input AD607 evaluation board (as received) r18 open r17 open vpos fdin r16 open vmid c20 short c19 anything r19 rsource fdin mod for dc coupled input
rev. 0 C20C AD607 figure 47. evaluation board layout
AD607 rev. 0 C21C the board provides sma connectors for the rf and lo port inputs, the demodulated i and q outputs, the manual gain con- trol (mgc) input, the pll input, and the power-up input. in addition, the if output is also available at an sma connector; this may be connected to the pll input for carrier recovery to realize synchronous am and fm detection via the i and q de- modulators, respectively. table iii lists the AD607 evaluation boards i/o connectors and their functions. table iii. AD607 evaluation board input and output connections reference connector approximate designation type description coupling signal level comments j1 sma frequency dc 400 mv this pin needs to be biased at vmid detector input and ac coupled when driven by an external signal generator. j2 sma power up dc cmos logic tied to positive supply by jumper j10. level input j3 sma lo input ac C16 dbm input is terminated in 50 w . ( 50 mv) j4 sma rf input ac C15 dbm max input is terminated in 50 w . ( 54 mv) j5 sma mgc input dc 0.4 v to 2.0 v jumper is set for manual gain control or (3 v supply) input; see table i for control voltage rssi output (gref = vmid) values. j6 sma if output ac na this signal level depends on the AD607s gain setting. j7 sma q output ac na this signal level depends on the AD607s gain setting. j8 sma i output ac na this signal level depends on the AD607s gain setting. j9 jumper ties gref na na sets gain-control scale factor (sf); to vmid sf = 75/vmid in db/v, where vmid = vpos/2. j10 jumper ties power-up na na remove to test power up/down. to positive supply t1 terminal pin power supply dc dc 2.7 v to 5.5 v positive input draws 8.5 ma at (vps1, vps2) midgain connection. t2 terminal pin power supply dc 0 v return (gnd)
rev. 0 C22C AD607 if the AD607s internal agc detector is used, then the gain/ rssi (pin 12) becomes an output and the rssi voltage appears across c12, which serves as an integrating capacitor. this volt- age must be monitored by a high impedance (100 k w minimum) probe. the internal agc loop holds the if voltage at ifop (pin 14) at 300 mv; in this application, about 6 db of attenua- tion is needed between pins ifop and dmip to avoid overload- ing the i and q demodulators. figure 48. evaluation board test setup hp 6632a programmable power supply 2.7v?v hp 3326 synthesized signal generator 10.710 mhz fluke 6082a synthesized signal generator 240 mhz hp 8656a synthesized signal generator 240.02 mhz AD607 evaluation board tektronix 11402a oscilloscope with 11a32 plugin hp 8656a synthesized signal generator 229.3 mhz data precision dvc8200 programmable voltage source hp 9920 ieee controller hp9121 disk drive mcl zfsc?? combiner ieee ?88 bus vpos fdin i output q output mgc lo rf s in operation (figure 48), the AD607 evaluation board draws about 8.5 ma at midgain (59 db). use high impedance probes to monitor signals from the demodulated i and q outputs and the if output. the mgc voltage should be set such that the signal level at dmip does not exceed 150 mv; signal levels above this will overload the i and q demodulators. the inser- tion loss between ifop and dmip is typically 3 db if a simple low-pass filter (r8 and c2) is used and higher if a reverse- terminated bandpass filter is used.
AD607 rev. 0 C23C outline dimensions dimensions shown in inches and (mm). 20-pin plastic ssop (rs-20) 1. lead no. 1 identified by a dot. 2. leads will be either tin plated or solder dipped in accordance with mil-m-38510 requirements 0.009 (0.229) 0.005 (0.127) 0.037 (0.94) 0.022 (0.559) 8 0 0.0256 (0.65) bsc 0.07 (1.78) 0.066 (1.67) 0.295 (7.50) 0.271 (6.90) 0.008 (0.203) 0.002 (0.050) pin 1 0.311 (7.9) 0.301 (7.64) 0.212 (5.38) 0.205 (5.207) 1 20 11 10
c2047C10C7/95 printed in u.s.a. C24C

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